1. Field of the Invention
The invention relates generally to Peripheral Component Interconnect Express (PCIE) and more specifically relates to systems and methods used to address issues stemming from resets of connections between non-PCIE host devices and PCIE bridges in a PCIE environment.
2. Discussion of Related Art
PCIE is a set of standards that define rules for serialized communication between electronic devices. PCIE devices may be used for any number of purposes within an electronic system. However, many electronic systems include more than just PCIE devices (i.e., these other devices support communication protocols such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), etc.). PCIE bridges are therefore often placed within an electronic system in order to facilitate communications between the PCIE and non-PCIE devices.
For example, a PCIE bridge may be used to carry communications between a SATA host and a PCIE storage controller managing one or more storage devices. The PCIE bridge may receive a SATA read request from a host, and may generate a corresponding PCIE Memory Read Request (MRd) for transmission to the storage controller. The PCIE bridge may then receive a PCIE Memory Read Completion (MRC) from the storage controller in reply to the MRd, and the MRC may include completion data (i.e., payload data) that was requested by the host. The completion data from the MRC is then provided to the host in a SATA-compatible communication for processing.
It is not uncommon for a SATA connection between a PCIE bridge and a host to be reset for any of a number of reasons. When the reset occurs, one or more MRCs may still be in the process of being generated for MRds that were sent out along the PCIE system before the reset. Unfortunately, once the connection has been reset, the host is unaware of the previous MRds that it triggered before the reset. Because of this, the host, upon receiving data for an MRC associated with an old MRd that was sent out prior to reset, may mistakenly assume that the data from the MRC corresponds to an MRd that was generated after the connection was reset. This means that the host will mistakenly assume that data received in response to an old request is actually for a new request, which is inaccurate. This in turn is likely to result in corruption of data on the system, which often is a fatal flaw in storage system environments that place a premium on data integrity.
As presently practiced in the art, PCIE requires that an idle period of about 160 milliseconds (ms) be implemented along a recently reset communication channel in order for any pending MRCs to clear out of the system. From this point forward, the system assumes that no MRCs are still being processed that relate to MRds sent before the connection was reset. However, this solution results in a number of problems. First, delaying processing for 160 ms along a communication channel with the host adds a substantial amount of latency to the system, and leaves processing resources idle that could otherwise be used to carry data between various components of the system. Second, even a delay as long as 160 ms does not guarantee that all MRCs relating to old MRds will be discarded by the system. If data from an MRC takes longer than 160 ms to get back to the host device, it will still interfere with processing on the system and remains likely to cause data corruption.
Thus it is an ongoing challenge to account for connection resets between PCIE bridges and non-PCIE host devices in an electronic system.